In the past, integrated circuits have been manufactured more or less solely by using a number of masks or reticles comprising a pattern of a layer in said integrated circuit. In today's integrated circuits the number of layers could be larger than 30. Said Masks or reticles may be prepared in lithographical manner by using for example electron beams or laser beams for exposing a layer of material sensitive for the type of beam chosen. The mask material is most commonly transmissive on top of one of its sides a thin layer of opaque material is attached. In said thin material the pattern of one layer of said integrated circuit is created. The mask has typically N times larger pattern than the pattern to be printed on the semiconducting substrate for forming said integrated circuit. The reduction in size is performed in a stepper, which uses the mask(s) for forming said integrated circuit.
More recently, the need to manufacture integrated circuits by means other than using a conventional mask has developed for a number of reasons, for example the price of manufacturing mask(s) has increased due to its complexity to manufacture, small-scale development which needs very small series of integrated circuits, etc.
Unfortunately, all of the present known techniques for forming integrated circuits without using conventional masks or reticles have drawbacks and limitations.
For example, most direct-writers known in the art are based on electron beams, typically so called shaped beams, where the pattern is assembled from flashes, each defining a simple geometrical figure. Other systems are known which use raster scanning of Gaussian beams. By using a conventional mask writer, which uses beams of electrons or laser beams for forming the pattern on a workpiece, is limited to relatively low scanning speeds, and, perhaps worst of all, can only scan a single dimension.
SLM writers disclosed in other patent applications, such as WO 01/18606 and U.S. patent application Ser. No. 09/954,721 by one of the assignees of the present invention and hereby incorporated by reference is related to raster scanning in the sense that it permits a bitmap pattern, but distinct by printing an entire frame of pattern in one flash instead of building the pattern from individual pixels.
A spatial light modulator (SLM) comprises a number of modulator elements, which can be set in a desired way for forming a desired pattern. Reflective SLMs may be exposed to any kind of electromagnetic radiation, for example DUV or EUV for forming the desired pattern on the mask.
A direct-writing pattern generator for writing certain layers in a semiconductor design directly from data would have a high value to the industry. However, the complexity of modern chips is extremely high and getting higher by every new technology generation. The direct-writer must write the complex pattern not one, but 100 times on a 300 mm wafer.
FIG. 1 depicts in simplified form a representation for a prior art direct writer that writes one chip 110 at a time with a particle beam 120.
FIG. 2a illustrates a representation of a conceived direct-writing system 200 with multiple e-beam columns 250, a pattern store 240, a rasterizing unit 230, a memory unit 220 and column buffers 210. FIGS. 1 and 2a are from material presented by Mark Gesley of ETEC Systems at the ISMT/SRC Maskless Lithography Workshop 2002 in August the same year. The presentation describes a conceived multiple micro-column e-beam system using a raster scan gray-scale principle. The micro-columns form a regular array with from 5×5 to 20×20 mm separation. The array covers a substantial part of the wafer's area and the stage is scanning only to fill the 5×5 mm (etc.) area. Over scanning into the next micro-column space can be used for redundancy. It is however unclear from the presentation how the information is presented internally. The image of the multiple micro-columns indicates that the same data is sent to each micro-column and the number of field is equal to the number of columns.
Researchers at UC Berkeley have explored another aspect of handling large data flows. One item to be handled by a direct-writer is the loading of data onto the transducers, here a micro-mechanical SLM. By compressing the pattern strongly it is possible to store on hard disks and decompress in several cascaded steps at the time of writing. FIG. 2b is an illustration of a parallel architecture according to UC Berkeley for handling large data flows. At least one step of decompression is done on the SLM chip. By this method both storage and transmission issues are thought to be solved.
Modern microelectronic designs are so complex that the sheer storage and transmission of the design files becomes a problem. When the design is flattened out, i.e., when its hierarchy is resolved, the data volume expands and finally the volume expands beyond all practical storage option when it is converted into bitmap. From a design file of typically 10–100 G bytes a bitmap volume of 1000 Tbyte is produced for a wafer. The figures are only an indication of the orders of magnitude and will of course change by wafer size and technology node. Only compression is not going to solve the bandwidth issues of the data flow, since data has to be processed and modified during conversion to bitmap data. An example is that overlap has to be removed and process bias added after the removal of the overlap.
What is needed is a method and apparatus, which creates pattern on a workpiece essentially faster than the prior art techniques and is capable to handle the large data flows necessary.